1. Field of the Invention
The present invention relates to data transmission systems and methods. More specifically, the present invention relates to systems and methods for encoding digital data at high speed to provide a balanced serial data stream that includes bit and frame synchronization control.
2. Description of the Related Art
The need to transmit large quantities of data rapidly from point to point led to the development of very high-speed communication links such as optical fibers and associated electro-optical components. In many such applications, it is necessary to serialize the data prior to transmission.
It is preferable, in the art, to encode a stream of data for transmission in such a manner that the data stream is balanced. "Balanced" means that over time the stream includes an equal number of logical one bits and logical zero bits. In electrical signal terms, a balanced data stream does not have a DC component whereas an unbalanced stream has a DC component.
Balanced data permits the use of AC-coupled circuits in the communication link. Many communication links do not perform satisfactorily, some do not perform at all, unless AC-coupled circuits can be used. For example, it may be necessary to use a transformer (an AC coupling device) to prevent ground loops and to reduce common mode signals. In addition, a laser element in a high-speed fiber optic transmitter requires a regulated drive current. If the laser carries balanced data, the average drive current is independent of the data and therefore is easier to regulate than would be the case if unbalanced data were transmitted. Also, it is easier to separate balanced data from DC bias currents in an optical receiver. Accordingly there was a need for a method of encoding digital data so that the resulting data stream is balanced before providing the data to a transmitter in a communication link.
Another need derives from the requirement that a receiver in a digital communication link be synchronized with an incoming digital signal so that it can extract frame and bit timing information from the signal. This timing information is then used to recover the actual data. Such synchronization may be accomplished, for example, by means of a phase-lock loop ("PLL") circuit such as that described in U.S. Pat. No. 4,926,447, the teachings of which are incorporated herein by reference.
It is also desirable to communicate various control signals to the receiver. These signals may convey additional information or they may be used to regulate the operation of the receiver itself.
A method of providing a balanced data stream is described in Carter, R. O., "Low-Disparity Binary Coding System," Electronic Letters, May 1965, Vol. 1, No. 3, pp 67-68. Briefly, groups of bits are inverted as needed to maintain a balance between the average number of logical one bits and logical zero bits carried by the communication link. An indicator bit is appended to each group to indicate whether that group is being transmitted in inverted form.
An improved version of this method, and apparatus for implementing it, are described in U.S. Pat. No. 5,022,051, the teachings of which are incorporated herein by reference. This patent also teaches appending a small plurality of M bits to each data word. These appended bits may be used, for example, to indicate whether the data bits have been inverted. In addition, the bits may carry a "master transition" which always occurs in the same relative position in each word. These bits are used by the receiver to establish synchronization with the incoming data stream.
A transition is defined by a change in the logic levels of two adjacent bits. The polarity of a transition is either positive-going, as in a change from a logical zero to a logical one, or negative-going.
Typically, it has been required that a master transition always have the same polarity. Two bits are required to define a master transition that always has the same polarity. The information content of a data stream could be increased by providing a master transition that could be of either polarity.
It was also desirable to provide a method of checking an incoming signal for errors. This has been done by transmitting additional bits, such as parity bits, that can be used by the receiver to determine whether the received signal contains any errors. However, these bits carry no primary information and using them results in some degradation of the maximum rate at which data can be transmitted.
Accordingly, there was a need for a way to encode data so as to provide a balanced data stream, that provided a high rate of data transfer, and that facilitated receiver synchronization and control and error checking.
The need in the art was addressed by U.S. Pat. No. 5,438,621, issued Aug. 1, 1995 to H. Thomas et al., and entitled DC-FREE LINE CODE AND BIT AND FRAME SYNCHRONIZATION FOR ARBITRARY DATA TRANSMISSION, (hereinafter the "Thomas" patent) the teachings of which are incorporated herein by reference. The Thomas patent provides a novel method of encoding digital data into a balanced data stream that affords a high rate of data transfer and that facilitates receiver synchronization and control and error checking with only a minimal reduction in the data rate. This coding scheme is also known as `CIMT`, (Conditional Invert Master Transition).
Briefly and in general terms, the CIMT method of encoding data according to the Thomas patent includes maintaining a cumulative polarity of bits which have previously been transmitted, forming a frame by combining a data word with a group of additional bits, using at least one of the additional bits to define a master transition in a fixed location in the frame, and setting the logical values of the combined bits such that the frame has a different polarity than the cumulative polarity.
As disclosed by Thomas et al., the "polarity" of a frame has one value (say, positive) if the frame contains more logical one bits than logical zero bits and a different value (negative) if the frame contains fewer logical one bits than logical zero bits. If the frame has equal numbers of logical one bits and logical zero bits, the polarity is considered to be neutral. Similarly, the cumulative polarity is positive if more logical one bits than logical zero bits have been transmitted, negative if fewer logical one bits than logical zero bits have been transmitted, and neutral if equal numbers of both kinds of bits have been transmitted.
In a preferred embodiment of the teachings of Thomas et al., a further bit was transmitted by encoding it into the additional bits as a "phantom" bit, often referred to as the flag bit. Thus, even though the further bit was not concatenated onto the bits to be transmitted, its logical value was carried by the additional bits and may be recovered by the receiver. This further bit may serve as another data bit to increase the data rate or it may be used for such other purposes as control or error checking, for example by varying its value from one frame to the next according to a predetermined error-checking pattern.
The frame polarity was set by Thomas opposite the cumulative polarity by inverting the logical values of the data bits and encoding the additional bits to indicate whether the logical values of the data bits have been inverted if the frame polarity would otherwise be the same as the cumulative polarity. If either the frame polarity or the cumulative polarity is neutral, the bits may be inverted or not as may be convenient.
In an alternative, if it was necessary to invert the logical values to maintain a balanced data stream, all the bits in the frame are inverted. In this case, the logical level of one of the additional bits could be used as an indicator of whether the bits have been inverted.
In another embodiment, the order of the bits is rearranged before transmission according to a predetermined pattern and reassembled after reception. An unauthorized receiver, not having the arrangement order, would not be able to reconstruct the data.
One or another of the bits adjacent the bits which define the master transition were preferably set to the same values as the bits which define the master transition from time to time as frames are transmitted so that the master transition is not always surrounded by other transitions. This tended to prevent the receiver from inadvertently staying locked onto a transition other than the master transition without detection of such an error.
Control words and fill words could be transmitted in addition to data words. A control word carries either information or control signals as desired. A fill word has only one transition in addition to the master transition and is used to establish synchronization and thereafter if necessary to maintain or reestablish synchronization. The fill words are balanced or are used in balanced pairs such that polarity need not be checked and the logical values of fill bits need not be inverted. The logical values of the additional bits indicate which type of word is being transmitted; in addition, a bit within a word, for example one or more bits in a control word, may be used to distinguish a control word from a fill word.
The master transition in the fill word typically was always of the same polarity. This facilitated synchronization of the receiver. After synchronization was attained, master transitions of either polarity were sufficient to maintain synchronization.
While Thomas et al. substantially addressed the need in the art for a way to encode data so as to provide a balanced data stream, that provided a high rate of data transfer, and that facilitated receiver synchronization and control and error checking, a need remains for further improvements in this area. Specifically, there has been a need to utilize the teachings of Thomas et al. in a simplex configuration, i.e., requiring no handshaking between the source and destination nodes. In a simplex configuration, it is difficult for a receiver constructed in accordance with the teachings of Thomas et al., to find the master transition, the point at which the cumulative polarity of the received signal changes from one state to the other.
Thus, a need remains in the art for a high-speed, reliable data transmission system and method using a CIMT coding scheme in a simplex configuration.